Question: ( 2 ) Which VHDL statement is not valid? a . abc < = a or b when c = 0 else a and b;

(2) Which VHDL statement is not valid? a. abc <= a or b when c =0 else a and b; b. abc <= a when c =1 else b; c. abc <= a or b when c =0 else a and b when c =1 else X when others; d. abc <="1101" when c =1 else 0;

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