20+ 2:37 < = Slides Cache Visualization CSE 351 23au Cache Visualization This homework is intended to help you prepare for Lab 4 by helping you understand intuitively how memory maps into the cache and, by extension, how sections of memory cause cache conflicts. With this knowledge, you will be able to write code that minimizes miss rates. You will need to use the 351 Cache Simulator with the following parameters: m = 6, C = 8 K = 2, E = 1 Write through Write-allocate Address width: 6 bits Cache size: 8 bytes Block size: 2 bytes Associativity: 1 way Write Hit: Write through All other settings at their default values Eviction: LRU On smaller screens, the 351 Cache Simulator may not display properly, but you can use the image below as a reference: AA Set 0 56 VT Cache Data OOO|| 0 Set 1 Set 2 Set 30 edstem.org m Physical Memory 0x00 20 f6 ef ea a2 5e 9f 1a 0x08 a2 d0 4fc4|a0|0c|f7 27 0x10 b8 bd 1a ca 35 95 cb 80 0x18 84 3f 02 4f 8e f3f6e5 0x20 cd 4a f6 48 1a 6f 7e 63 0x28 e9 36