$[30$ points$]$

A small $16-$bit address space special$-$purpose processor may be equipped with one of two tiny direct$-$mapped caches, $C1$ or $C2,$ each of which has a total capacity of $64$ bytes. C$1$ has a blocksize of $4$ bytes $($which corresponds to the size of an integer on this system$)$ while C$2$ has a blocksize of $16$ bytes.

$($a$)$ What are the cache parameters $($m$,$ C$,$ B$,$ E$,$ S$,$ t$,$ s$,$ b$)$ for C$1$ and C$2?$

$($b$)$ Consider that the following sequence of addresses are read, $($where the size of the data path equals the blocksize$)$: BA$00,$ BA$04,$ AA$08,$ BA$05,$ AA$14,$ AA$11,$ AA$13,$ AA$38,$ AA$09,$ AA$0$B$,$ BA$04,$ AA$2$B$,$ BA$05,$ BA$06,$ AA$09,$ AA$11.$

For each cache option, specify which references are hits and which are misses, and show the final data content of the caches