$3)(10$ points$)$ Next, add a $16$K RAM unit corresponding to the memory address range $$4000$ to $$7$FFF$.$ Show the logic to generate the CE signal$($s$)$ for this RAM, which should be active low, if $2$K x $8$ RAM chips are used. Draw and test the complete circuit in Logisim within the $"$Q$3"$ subcircuit in the provided file.

$($Hint: Note that a $2$K x $8$ RAM chip has a capacity of $2048$ bytes, so you will need to use an array of eight of these chips to create a single $16$K x $8$ memory unit. Instead of using traditional logic gates to generate separate CE signals for all eight chips, I suggest that you use a $3$:$8$ decoder in your design. The chip$-$enable signal $!$CE$0$ should correspond to the chip at the bottom of this address range, and the chip$-$enable signal $!$CE$7$ should correspond to the chip at the top of this address range. When adding the decoder in Logisim, be sure to set the "Three$-$State" property to $"$No$,"$ and the "Disabled Output" property to "Zero," so that the outputs function as expected when the entire RAM unit is disabled. The "Enable" input of the decoder should be used to disable all outputs when the active address is outside the specified range; since Logisim's decoder outputs are active$-$high, you may need to use NOT gates to change the outputs to active$-$low.$)$