Question: 3 . 3 A faster hardware implementation of the MULT instruction is designed and simulated for a proposed machine M 3 , also clocked at

3.3

A faster hardware implementation of the MULT instruction is designed and simulated for a proposed machine M

3,

also clocked at

80

MHz

.

A speedup of

10 %

over M

1

is observed. Is this possible or is there a bug in the simulator? If it is possible, how many cycles does the MULT instruction take in this new machine? If it is not possible, why is this so

?

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