Question: ( 3 ) [ 4 + 2 + 4 + 2 + 2 ] You are given the following code to analyze: 1 . int

(3)[4+2+4+2+2] You are given the following code to analyze:
1. int x[2][128];
2. int i, sum =0;
3. for (i =0; i <128; i++)
4. sum += x[0][i]* x[1][i];
Assume the code is executed under the following conditions:
sizeof(int)=4
Array x begins at mem. addr. 0x0 and is stored in row-major order.
Cache initially empty
Only mem. accesses are to elements of x. Rest of the variables are in
registers.
(a) Case 1: Assume cache is 512 bytes, direct-mapped, with 16 byte blocks.
What is the miss rate? Explain.
(b) Case 2: What is the miss rate if the cache size is doubled (becomes 1024
bytes). Explain.
(c) Case 3: If the cache were to be a 512 byte, two-way set-associative cache
using an LRU replacement policy, with 16 byte cache blocks. What is
the cache miss rate? Explain.
(d) For case 3, will a larger cache size help reduce the miss rate? Why or
why not?
(e) For case 3, will a larger block size help reduce the miss rate? Why or
why not?

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