$3\mathrm{.}4$ Consider a hypothetical microprocessor generating a $16-$bit address $($for example, assume that the program counter and the address registers are $16$ bits wide$)$ and having a $16-$bit data bus. interrupt handler interrupt service routine $($ISR$)$ lane memory address register $($MAR$)$ memory buffer register $($MBR$)$ multilane distribution packets PCI Express $($PCIe$)$ peripheral component interconnect $($PCI$)$ phit QuickPath Interconnect $($QPI$)$ root complex system bus $3\mathrm{.}7/$ Key Terms, Review Questions, and Problems $131$ a$.$ What is the maximum memory address space that the processor can access directly if it is connected to a $"16-$bit memory"? b$.$ What is the maximum memory address space that the processor can access directly if it is connected to an $"8-$bit memory"? $c.$ What architectural features will allow this microprocessor to access a separate $"$I$/$O space"? d$.$ If an input and an output instruction can specify an $8-$bit I$/$O port number, how many $8$bit I$/$O ports can the micrqprocessor support? How many $16-$bit I$/$O ports?