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Q1. Up-Down Counter Design
(20 points)
Design a 4-state synchronous counter with a Reverse input (R), the counter produces the sequence: 0,1,2,3 then repeats the count when R=0. When R=1 the count sequence is 3,2,1,0, then repeats. The counter is to be implemented using JK flip-flops. The output Z indicates whether the counter is counting UP or DOWN.
a) Complete the state transition table below
b) Derive the input equations for each JK flip-flop in minimal sum-of-products form
c) Show the equation for the output Z
\table[[PS,IN,NS,OUT,JK FFs,],[Q1,Q0,R,Q1+,Q0+,Z,J1,K1,J0,K0,],[0,0,0,0,1,0,0,d,1,d,],[0,0,1,1,1,1,,,,,],[,,,,,,,,,,],[,,,,,,,,,,],[,,,,,,,,,,],[,,,,,,,,,,],[,,,,,,,,,,]]
J1=
K1=
J0=
K0=
3
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