3

a)

b)

How does the load enable for DR (DRin) need to behave relative to the MemRd0 and MemRd1 control signals? You can answer with a schematic or a logic equation.

The following picture shows two of these 4-bit wide memories, and one Data Register (DR) that can be used to capture a value read out of either memory. MEM O MEM 1 Data Data 4 X4 X4 DRin DR Assume we have two control signals, MemRdO and MemRd1, which indicate that we want to read a value out of either Memo or Mem1, respectively, and cause that value to be loaded into DR. Draw a schematic that fills in the gap, showing some means for allowing 4-bit data values from either memory to be connected to DR. The controls for your schematic should show the use of MemRdO and MemRd1. The following picture shows two of these 4-bit wide memories, and one Data Register (DR) that can be used to capture a value read out of either memory. MEM O MEM 1 Data Data 4 X4 X4 DRin DR Assume we have two control signals, MemRdO and MemRd1, which indicate that we want to read a value out of either Memo or Mem1, respectively, and cause that value to be loaded into DR. Draw a schematic that fills in the gap, showing some means for allowing 4-bit data values from either memory to be connected to DR. The controls for your schematic should show the use of MemRdO and MemRd1