(3) (a) Conside r a high performance Cache Memory and it has the following blocks loaded initially with (S+5 10 points the intital LRU counter priority set as shown below in the figure. A 7 E13 G 2 What will be the final sequence of sequence of requests A, B, A, D, K. Indicate how in each access the LRU counter will change its value leading to the final memory blocks in the Cache. the Memory Blocks after the Processor makes the following (b) Consider L1, 12 Cache maintain Inclusion property and the following condition happens Dirty Block replaced from L1 (Write Back Cache) Write back can be L2 hit Consider L1, L2 Cache do not maintain Inclusion property the following condition happens Dirty Block replaced from L1 (Write Back Cache) Write back can be L2 hit miss