3. An instruction may do nothing during a stage; in this case, we say that the instruction is not active in the stage. For instance, add $S0, $S1,$S2 is not active in the state MEM. For each of the following instructions, pls tell me the instruction is active or not in each of the five stages IF, ID, EX, MEM, WB. It is helpful to look at the pipeline datapath I draw in class. (1). add $S0, $S1,$S2 (2). lw $S0, 4($sp) (3). beq $S0, $S1, LOOP

4. Explain why we need 97 bits (instead of 96 bits) for the EX/MEM buffer