$3-$ Consider a critical section of a code that is protected by lock and unlock primitives as shown below. Suppose

the two processors $(P0$ and $P1)$ running the code are both trying to acquire a lock at address $0x100($i$.$e$.,$ register

R$1$ holds the address $0100).$ The SMP uses the MESI cache coherence protocol and implements cache$-$to$-$cache

transfer. Determine the total number of cycles required for both processors to execute their critical sections.

Initially, only the main memory has the block that contains the lock, and thus the block in both caches are in

Invalid $($I$)$ state. Assume the following:

The processors acquire the lock in order $($i$.$e$.,11-$sc pair for P$0$ occurs before $11-$sc pair for P$1)$

PrRd and PrWr misses, if satisfied by the main memory and cache $($i$.$e$.,$ cache$-$to$-$cache transfer$),$ require

$N_{\text{m}\text{e}\text{m}\text{o}\text{r}\text{y}}=80$ and $N_{\text{c}\text{a}\text{c}\text{h}\text{e}}=35$ cycles, respectively.

PrWr hits that cause invalidations incur $N_{\text{i}\text{n}\text{v}\text{a}\text{l}\text{i}\text{d}\text{a}\text{t}\text{e}}=15$ cycles.

PrWr hits that do not cause any bus activity incur no stalls.

Assume the critical section is $1200$ cycles long.

lock: