3. Consider a version of our five stage pipeline that performs Branch Target Address (BTA) calculation...

 

Transcribed Image Text:

3. Consider a version of our five stage pipeline that performs Branch Target Address (BTA) calculation in the ID stage and branch outcome determination in the EX stage. This means that the BTA is available one cycle before the branch outcome is known. Suppose that 25% of all instructions are branch instructions and that 60% of branches are taken. a. If the pipeline stalls until both the BTA and branch outcome are known for a branch instruction, what is the per-instruction branch penalty for the processor (in cycles)? b. If the pipeline uses static, branch-not-taken prediction, what is the per- instruction branch-penalty for the processor? C. Now assume that the processor uses branch-not taken prediction during the first cycle following a branch, and then switches to branch-taken prediction for the second cycle, since the BTA is available at this point. What is the per-instruction branch penalty for the processor in this case? d. Which of these three strategies results in the lowest branch penalty? 3. Consider a version of our five stage pipeline that performs Branch Target Address (BTA) calculation in the ID stage and branch outcome determination in the EX stage. This means that the BTA is available one cycle before the branch outcome is known. Suppose that 25% of all instructions are branch instructions and that 60% of branches are taken. a. If the pipeline stalls until both the BTA and branch outcome are known for a branch instruction, what is the per-instruction branch penalty for the processor (in cycles)? b. If the pipeline uses static, branch-not-taken prediction, what is the per- instruction branch-penalty for the processor? C. Now assume that the processor uses branch-not taken prediction during the first cycle following a branch, and then switches to branch-taken prediction for the second cycle, since the BTA is available at this point. What is the per-instruction branch penalty for the processor in this case? d. Which of these three strategies results in the lowest branch penalty?