Question: 3. Consider the pipelined processor below A RO A2 RD2 Fetch Decode Assume that this processor is going to run the following program: 1. add

3. Consider the pipelined processor below A RO A2 RD2 Fetch

3. Consider the pipelined processor below A RO A2 RD2 Fetch Decode Assume that this processor is going to run the following program: 1. add r11, r2, r3 2. lw r12,4 (r4) 3 and r13,r6,r7 4. xorr14,r13, r5 5. addi r5,r3,100 6. swr3,100 (r6) Assume that in cycle 5 instruction 1 is in the writeback stage, while instruction 5 is in the fetch stage. Give the values of control signals A to D in this cycle: A: List what instructions will be in each stage in cycle 6: C: D: Fetch Memory Writeback

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