$3-$ Deep learning accelerator Design and implement a verilog module called $$perceptron$.$ We will use fixed point format in our simple single layer perceptron. It should follow the following specification. Top level Port name Direction Width Description rst$\_$n Input $0$:$0$ Active low reset clk Input $0$:$0$ Clock x$1$ Input $7$:$0$ Signed fixed point x$2$ Input $7$:$0$ Signed fixed point valid$\_$in Input $0$:$0$ Inputs valid y Output $0$:$0$ Unsigned $(0$ or $1)$ y$\_$valid Output $0$:$0$ Y valid, driven by design Perceptron should also contain internally $($Read Only Memory $-$ ROM$)-$ b reg $7$:$0$ Bias $-$ Signed fixed point w$1$ reg $7$:$0$ Weight $-$ Signed fixed point w$2$ reg $7$:$0$ Weight $-$ Signed fixed point Please use the following values signed $[7$:$0]$ w$1=8\text{'}$sb$00000010$; signed $[7$:$0]$ w$2=8\text{'}$sb$11111110$; signed $[7$:$0]$ b $=8\text{'}$sb$11111101$; Fixed point x$1,$ x$2,$ b$,$ w$1,$ w$2$ all have an implicit decimal point in the middle of the $4$ least significant bits i$.$e$.$ b$/$w bit $2$ and bit $1.$ Hence, every signed fixed point number $=($Value if it were a signed integer$)/4,000001012=1\mathrm{.}25(=5/4)111110002=-2(=-8/4)111110102=-1\mathrm{.}5(=-6/4)$ etc You may use the same adder and multiplier that work with signed integers, but will need to account for the decimal point. If we add two numbers of the above type, the decimal point is still $2$ places from the least significant bit $($LSB$).$ But if we multiply two such numbers, the implicit decimal point is $4$ places from the least significant bit, so to get the correct fixed point product, we need to shift it right by $2$ in this case. Working $-$ The perceptron must be pipelined $($each stage $1$ clock cycle and computation on new inputs begins every clock cycle$).$ In first stage, it uses $2$ signed multipliers to calculate the products p$1=$ w$1*$x$1$ and p$2=$ w$2*$x$2.$ In the second stage, it adds the p$1,$ p$2$ and b to get an intermediate signed output $-$ s$.$ For a deep learning accelerator we will over provision, hence, we will use multiple multipliers and adders such that all multiplications may be finished in $1$ stage $($clock cycle$)$ and all additions may be finished in one stage $($clock cycle$).$ For now, we just want to get it functionally correct and pipelined. At a later point we may want to refine the design to be our accelerator. You may use $*$ and $+$ sign now, but at some point we may want to use the IP components and may want to pipeline the multiplier for best performance. You may save your self future effort by using the library components now itself $($be aware that will change clock cycles, no extra marks$).$ After the addition $($after the $2$nd stage$),$ it asserts or de$-$asserts y based on $-$ y $=1$ if s $>=00$ Otherwise Hence, latency $=2$ Clock cycles You must use internal registers of appropriate size to contain the complete intermediate results.