$3$: Inside your Q$2$ folder, you are going to use a different approach to describe the $2-$digit BCD adder. No longer using hierarchical design by instantiating the $1-$digit BCD adder as you did in Q$1,$ here you are expected to translate an algorithm like the one represented by the following pseudo$-$code, into SystemVerilog code.Before your translation, take a moment to think about what circuit could be used to implement this pseudo$-$code? It is reasonably straightforward to see that lines $1,9,10,$ and $18$ represent adders, lines $28$ and $11-17$ correspond to multiplexers, and testing for the conditions T$\_(0)>9$ and T$\_(1)>9$ requires comparators.

Now perform the following steps to describe the $2-$digit BCD adder by translating the given pseudo$-$code:

Create a SystemVerilog module TwoDigit$\_$BCD$\_$Adder$2.$sv that implements the algorithm shown above. Include the testbench you used in Q$1$ to test this module using ModelSim. You need to create correct runlab. do and wave. do files to run the simulation.

Create a new Quartus project called Q$2.$ Copy your top$-$level module from Q$1$ here and rename it to

Q$2.$sv$.$ Use the same switches, lights, and displays as in Q$1.$ Compile your circuit.

Use the Quartus RTL Viewer tool to examine the circuit produced by compiling your SystemVerilog code. Take screen shots of RTL view at hierarchical levels, named as Q$2$rtlview$1.$png$,$ Q$2$rtlview$2.$png$,$ and so on$.$ Compare the circuit to the one you designed in Q$1,$ and comment on the comparison results at the initial comments block of TwoDigit$\_$BCD$\_$Adder$2.$sv $.$

Download your circuit onto the DE$2$ board and test it by trying different values for numbers $A_1{A}_0$ and $B_1{B}_0.$

$4$: Check and zip both Q$1$ and Q$2$ folders, you will get a zip file named HW$4.$zip. Submit HW$4.$zip to Canvas by $11$:$59$ pm$,$ Sunday $\frac{04}{28}.$