$3.$ SRAM

You are provided with a $8$x$8$ SRAM chip with the following specifications: Inputs: $3$ address lines $($A$0,$ A$1,$ A$2),8$ data lines $($D$0-$D$7),$ and control inputs for Chip Select $($CS$)$ and Write Enable $($WE$).$ Outputs: $8$ data output lines $($O$0-$O$7),$ which are gated with tri$-$state buffers. The outputs are in high$-$impedance $($hi$-$Z$)$ when CS $\backslash (=1\backslash )$ or in write mode.

A$.$ Using only two such RAM chips, implement an $\backslash (8\backslash$times $16\backslash )$ bit RAM circuit

B$.$ Using only two such RAM chips and a decoder, implement a $16$x$8$ bit RAM circuit.

C$.$ Using only eight such RAM chips and a decoder, implement a $\backslash (32\backslash$times $16\backslash )$ bit RAM circuit.