3. Suppose that a 16M x 16 main memory is built using 256K 16 RAM chips and memory is Word-addressable.

d) Display the address format using both high order and low order interleaving.

4. A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory.

a) How many bits are needed for the opcode?

b) How many bits are left for the address part of the instruction?

c) What is the maximum allowable size for memory?

d) What is the largest unsigned binary number that can be accommodated in one word of memory?

5. Explain the steps of the fetch-decode-execute cycle. Your explanation should include what is happening in the various registers.

6. Write the RTL logic for all the instructions.