$3.$ The figure shown shows the $80286$ buffered bus, two ROM chips $27256(32$ K $*1$ Byte chip$)$ and two SRAM chips with part number HMN$2$M$8$D $(2$ M$*1$ Byte chip$).$ It is required to interface the RAM chips at the starting address $400000$ H and the ROM chips at starting address FE$0000$H$.$ Show how to interface these chips at the specified addresses. $($Add any decoding chips or logic gates you need$).$ Write in the following table the starting and ending addresses for each chip. Write on each arrow of the chips the range of address and data required for each chip.

BHE

M$/$O$"$

MRDC$\backslash$#

MWTC$\backslash$#