3. The processor for which you are designing your application as L1i and L1d virtual caches.

a. What type of data does each cache hold? [2 points]

b. Describe in detail the activities of the cache + memory system when executing the instruction [3 points] LOAD virtual address, register

c. Assume that the above instruction is executed many times in a loop, and that the instruction itself is in the cache. Also assume that memory access costs s, and cache access costs /15 s. What cache hit rate for virtual address is required for the memory system to run 5 times faster than with no caching at all? Show your work. [7 points]

d. Suppose we have a memory system that has a main memory, a single-level cache, and demand paging virtual memory. The three levels of the memory system have the following access times:

Cache 2ns Main memory

100ns

Paging disk 10ms

i. The cache has a 95% hit rate. What is the effective memory access time if we consider only the cache and main memory and ignore page faults and disk access times? [3 points]

ii. Now recalculate the effective memory access time assuming the same cache hit rate (95%) plus a page fault rate of 0.001% (i.e., 99.999% of the memory accesses succeed without producing a page fault). [5 points]