3. Write structural VHDL code to implement 4-bit shifter below. [10 pts] w3 ri 7 S, AO A1 A2 A3 A0 A1 A2 A3 A0 A1 A2 A3 A0 A1 A2 A3 S1 y2 yl entity shifter is Port (w3, w2, w1, wo : in STD_LOGIC; s1, so : in std_logic; y3, y2, yi, y0 : out STD-LOGIC); end shifter rchitecture Behavioral of shifter its omponent mux41 is Port ( A0, A 1, A2, : in STD_LOGIC; S1, SO: in STD_LOGIC; Y: out STD LOGIC) component