3.13 25] In this exercise, you wi explore performance trade-offs between three processors that each employ different types of multithreading. Each of these processors is superscalar, uses in-order pipelines, requires a fixed three- cycle stall following all loads and branches, and has identical L1 caches. Instruc- tions from the same thread issued in the same cycle are read in program order and must not contain any data or control dependences. Processor A is a superscalar SMT architecture, capable of issuing up to two instructions per cycle from two threads. Processor B is a fine MT architecture, capable of issuing up to four instruc- tions per cycle from a single thread and switches threads on any pipeline stall