3.16 Tomasulos algorithm has a disadvantage: only one result can computer per clock per CDB. Use the hardware configuration and latencies from the previous question and find a code sequence of no more than 10 instructions where Tomasulo's algorithm must stall due to CDB contention. Indicate where this occurs in your sequence. FP type Integer FP adder FP multiplier Cycles in EX 1 10 15 Number of FUS Number of Reservation Stations 1 5 1 3 1 2 . Assume the following: Functional units are not pipelined. There is no forwarding between functional units; results are communicated by the common data bus (CDB). The execution stage (EX) does both the effective address calculation and the memory access for loads and stores. Thus, the pipeline is IF/ID/IS/EX/WB. Loads require one clock cycle. The issue (IS) and write-back (WB) result stages each require one clock cycle. There are five load buffer slots and five store buffer slots. Assume that the Branch on Not Equal to Zero (BNEZ) instruction requires one clock cycle