. (32 pts): The provided synchronous datapath is to be used to do the following calculation using a 4-bit unsigned integer IN: IN[3:0] OUT (2 x IN) IN Each data bus is 4 bits wide. The provided control signals are driven by the control unit (not shown here). RI and RO are registers with synchronous parallel load capability. Other blocks are combinational. The 4 bit ALU performs the following functions based on input F: CLK RI (4 bit) ALU OUT FI1:0] ALU Function EO load DI7:0 RO (4 bit) A B OUT[3:0] A B (addition) i. (16 pts) If IN 6 (hexadecimal), complete the below simulation waveforms in minimum number of clock cycles, indicating the values required from the control signals and data signals at each clock cycle in order to calculate OUT correctly. Enter the values of the multi-bit signals (IN, F, RI, ALU_OUT, OUT) in hexadecimal. Assume the propagation delays are all 0 (zero). Stop simulation waveforms when the 4 bit result is obtained for OUT computation. Calculate and show all arithmetic values (in hexadecimal format). CLK IN[3:0]o ALU OUTI3:0] EO OUTI3:01 o