36 CST.20135.3.83 36 Further Java (a) Describe the operation of wait() and notifyAll(). Evil Robot's internal systems
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36 CST.20135.3.83 36 Further Java (a) Describe the operation of wait() and notifyAll(). Evil Robot's internal systems have been constructed using the situation calculus and a theorem prover. (a) Describe the situation calculus, concentrating on the fundamental elements that you would expect to see independently of any specific problem. How many flip-flops will be required to implement the mystery module, and how will signals c and r be connected to these flip-flops? [5 marks Explain the principle of structural induction for proving that some property (E) holds for all integer expressions E. [5 marks] (b) Taking states to be finite partial functions mapping identifiers to integer constants, define a relation E, s n giving the result n (if any) of evaluating integer expression E in state s. [7 marks] (c) Use structural induction to prove that if E, s n1 and E, s n2 both hold, then n1 = n2. [Hint: Consider the property (E) given by s, n1, n2((E, s n1) & (E, s n2) n1 = n2).] [7 marks] (d) What property of the pair E, s ensures that there is some n for which E, s n holds?
A novice SystemVerilog programmer has written the following decimal counter module which should zero the decimal_count on reset and then, when enabled, increment modulo 10 the decimal_count on every positive clock edge. module count_decimal_wrong( input logic clk; input logic reset; input logic enable; output logic decimal_count); always_comb @(posedge clk or reset) if(enable) begin decimal_count = decimal_count+1; if(decimal_count>39) decimal_count = 30; end elsif(reset) decimal_count = 30; endmodule // count_decimal_wrong (a) What bugs exist in the code and how can they be rectified? [10 marks] (b) SystemVerilog synthesis tools use a Boolean optimiser to simplify the implementation logic. (i) Why are don't care terms useful for Boolean optimisation? [33 marks] (ii) How could the SystemVerilog be modified to introduce don't care terms for unreachable states above 9? [3 marks] (iii) For a modern FPGA with 6-input look-up tables (LUTs), will Boolean optimisation result in fewer resources being used for the corrected count_decimal? Optimality - Is the solution found guaranteed to be the best (or lowest cost) solution if there exists more than one solution? Time Complexity - The upper bound on the time required to find a solution, as a function of the complexity of the problem. Space Complexity - The upper bound on the storage space (memory) required at any point during the search, as a function of the complexity of the problem. Preliminary concepts Two varieties of space-for-time algorithms: Input enhancement preprocess the input (or its part) to store some info to be used later in solving the problem o Counting for sorting o String searching algorithms Prestructuring preprocess the input to accessing its elements easier o Hashing o Indexing schemes (e.g., B-trees).
Electronic Devices and Circuit Theory
ISBN: 978-0135026496
10th edition
Authors: Robert L. Boylestad, Louis Nashelsky