$(40$ pts$)3.$ Consider the memory bit pattern below to be stored on a fixed $\backslash (4\backslash$times $4\backslash )$ read$-$only memory $($ROM$)$ device.

$($a$)$ Sketch the memory circuitry which implements this memory array by using NMOS NOR ROM design. What logic function is performed by column $\backslash (\backslash$mathrm$\{$C$\}\_\{1\}\backslash )?$

$($b$)$ Sketch the memory circuitry which implements this memory array by using CMOS NAND ROM design. What logic function is performed by column $\backslash (\backslash$mathrm$\{$C$\}\_\{3\}\backslash )?$