4. [10 points.] Answer the following: (a) The equivalent gate count for a piece of Verilog code is 500 and the equivalent gate count for another piece of Verilog code is 40,000. If both pieces of Verilog code are separately synthesized into an FPGA, is there a difference in the size of the two bitstreams? Give reason for your answer. (b) For thefollowing Verilog code snippets, starting from time t0 draw the waveforms of a and b with respect to time. Assume that at time t0 a rising event occurs on clk. When we enter the always block, assume that a and b are in an X state. Explain the reason for the difference between the waveform of the two code snippets.| Code A always (posedge clk) begin b #1 1; end Code B always@ (posedge clk) begin #2 #2 1; 0; a(z end 4. [10 points.] Answer the following: (a) The equivalent gate count for a piece of Verilog code is 500 and the equivalent gate count for another piece of Verilog code is 40,000. If both pieces of Verilog code are separately synthesized into an FPGA, is there a difference in the size of the two bitstreams? Give reason for your answer. (b) For thefollowing Verilog code snippets, starting from time t0 draw the waveforms of a and b with respect to time. Assume that at time t0 a rising event occurs on clk. When we enter the always block, assume that a and b are in an X state. Explain the reason for the difference between the waveform of the two code snippets.| Code A always (posedge clk) begin b #1 1; end Code B always@ (posedge clk) begin #2 #2 1; 0; a(z end