Question: 4) 1201 Consider the following sequential circuit with two negative-edge-triggered JK flip-flops. Q1 Q2 Ql I CK K 02 Q2 CLR 12 CK K2 Clock

4) 1201 Consider the following sequential circuit with two negative-edge-triggered JK flip-flops. Q1 Q2 Ql I CK K 02 Q2 CLR 12 CK K2 Clock 4.a) 121 Complete the timing diagram for the above circuit. CLR Clock J1 KI Qi J2 K2 Q2 -19

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