4) (20 pts) Hardware pipelining is a common method to achieve faster clock frequencies by dividing operations into multiple stages, which are separated by registers. Assume you have a combinational circuit realizing a function F. The critical path delay of this circuit is 1000ps. You are asked to use a 300MHz clock for this circuit. Show how you would pipeline this circuit F. How many clock cycles would be your latency for the new circuit for F? What is the latency in time? (Assume that setup time, hold time and propagation delay of FF is 0)