4. [50] Cypress Semiconductor has two 4 Mib asynchronous SRAM chips with a maximum t = minimum trc of 55ns. One provides x8 bits of data at a time, the other x16 a. [10] What is the organization of the two chips? Do not use a calculator. Show your work. b. [10] What are the effective bandwidths of the two devices? Show your work c. [10] You're building a system that accesses memory sequentially (one byte at a time) but needs 30 MB/s of memory bandwidth. Is this possible using the x16 devices? If not, why not? If so, how? Be quantitative. Do not use a calculator. Show your work. d. [10] is this possible using the x8 devices? If not, why not? If so, how? Be quantitative. Do not use a calculator. Show your work e. [10] ignoring control, power, and ground pins, discuss the trade-offs in pin count between a 4Mib SRAM organized as a x device or as a x16 device. Assume data pins are bidirectional. 4. [50] Cypress Semiconductor has two 4 Mib asynchronous SRAM chips with a maximum t = minimum trc of 55ns. One provides x8 bits of data at a time, the other x16 a. [10] What is the organization of the two chips? Do not use a calculator. Show your work. b. [10] What are the effective bandwidths of the two devices? Show your work c. [10] You're building a system that accesses memory sequentially (one byte at a time) but needs 30 MB/s of memory bandwidth. Is this possible using the x16 devices? If not, why not? If so, how? Be quantitative. Do not use a calculator. Show your work. d. [10] is this possible using the x8 devices? If not, why not? If so, how? Be quantitative. Do not use a calculator. Show your work e. [10] ignoring control, power, and ground pins, discuss the trade-offs in pin count between a 4Mib SRAM organized as a x device or as a x16 device. Assume data pins are bidirectional