$4.$ For the unsigned addition of the given bit$-$pattern pair, identify the overall delay $($e$.$ the delay at which all the outputs of the circuit are finalized$)$ experienced in the case of each unsigned adder circuit mentioned below $($carry$-$in to the first bit position$=0$ in each case$).$ Assume that the delay due to one level of gates is D$.$ Also, assume that inverted versions of signal variables are already available $($i$.$e$.$ ignore inverter delays$).$ Furthermore, assume unlimited fan$-$in$.$

$\backslash (\backslash$begin$\{$array$\}\{$llllllllllllllll$\}1$ & $1$ & $0$ & $0$ & $1$ & $0$ & $1$ & $1$ & $1$ & $0$ & $1$ & $0$ & $0$ & $0$ & $1$ & $1\backslash$end$\{$array$\}\backslash )$

$1.$ RCA

$2.$ CCA

$3.$ BCLA with block size $\backslash (=8\backslash )$

$4.$ RCA$-$BCL adder with block size $\backslash (=8\backslash )$

$5.$ CSA with block size$=2$

$6.$ CSelA with block size$=8.$ Assume that the first block is implemented as an RCA

$5.$ For the $8-$bit $2\text{'}$s complement adder$/$subtractor$,$ find the overall worst$-$case delay $(\backslash ($ e $\backslash ).$ the delay at which all the outputs of the circuit are finalized$).$ Assume that the core unsigned adder is implemented using RCA logic. Assume that the delay due to one level of gates is D$.$ Also, assume that inverted versions of signal variables are already available $($i$.$e$.$ ignore inverter delays$).$ Furthermore, assume unlimited fan$-$in$.$