4. Implement the following high-level code segment using the slt instruction. Assume the integer variables g and h are in registers $80 and $sl, respectively. if (g>h) g=g - 1; else h=h+1; 5. Modify the single-cycle MIPS processor to implement the instruction slti. See Appendix B (in the textbook) for a deinition of the instructions. Mark up a copy of Figure 7.11 (in the textbook) to indicate the changes to the datapath. Name any new control signals. Mark up a copy of the Table 1 below to show the changes to the main decoder. Describe any other changes that are required. Table 1 Main decoder truth table to mark up with changes Instruction Opcode RegWrite Reg Dst ALUSE Branch MemWrite Memtokes ALUOP R-type 000000 100011 1 0 0 0 10 1 0 1 0 0 1 00 101011 0 X 1 0 1 00 beg 000100 0 X 0 1 0 X 01 6. A cache has the following parameters: b, block size given in numbers of words; S, number of sets; N, number of ways;and A, number of address bits. A 16-word cache has the parameters given above. Consider the following repeating sequence of lw addresses (given in hexadecimal) and cache conigurations: 74 AO 78 38C AC 84 88 8C 70 34 38 13C 388 18C The cache capacity is still 16 words. Assuming least recently used (LRU) replacement for associative caches, determine the efective miss rate if the sequence is input to the following caches, ignoring startup effects (i.e., compulsory misses) (1) two-way set associative cache, b = 2 words (2) direct mapped cache, b = 4 words