$4)$ The binary storage cell is the basic building block of a memory unit. The equivalent logic of a binary cell that stores one bit of information is shown in the figure below. The storage part of the cell is modeled by an SR latch with control input $($see Textbook Chapter $5\mathrm{.}3)$ and associated logic gates.

a$)$ Implement a simple binary cell $($BC$)$ that has equivalent circuit in the figure above in VHDL$.$ Test your design with following cases:

$-$ Input : $0,$ Select : $1,$ Read$/$Write : $0$

$-$ Input : $1,$ Select : $0,$ Read$/$Write : $0$

$-$ Input : $1,$ Select : $1,$ Read$/$Write : $1$

$-$ Input : $1,$ Select : $1,$ Read$/$Write : $0$

$-$ Input : $1,$ Select : $1,$ Read$/$Write : $1$

$-$ Input : $0,$ Select : $0,$ Read$/$Write : $0$

$-$ Input : $1,$ Select : $1,$ Read$/$Write : $1$

b$)$ Implement a small RAM which consists of $4$ words of $4$ bits using required amount of BCs$,$ decoder$($s$)$ and other necessary logic gates in VHDL $($see Textbook Chapter $7\mathrm{.}3).$

c$)$ Test your RAM design by writing words $\text{'}1\text{'},\text{'}9\text{'},\text{'}0\text{'},\text{'}2\text{'}($in binary$)$ to consecutive addresses from $0$ to $3.$ After $4$ write operations, apply read operations to the memory addresses in following order: $\backslash (3,2,0,1,3,2,0,1,3,2,0,1.\backslash ).$