4. Using the concepts we discussed in class, show how it is possible to construct a 3-input NAND gate and a 3-input NOR gate from CMOS transistors. NOTE this does not involve connecting separate gates a) Draw the schematic of both the 3-input NAND gate and the 3-input NOR gate b) Explain how it is possible to construct an n-input gate. How many transistors (including both PMOS and NMOS) are needed with respect to n? c) Why should we expect longer circuit delays in our gates as n increases? It may be helpful to draw the structure of the NMOS and PMOS transistors to explain