4. Using the dataflow modeling, and consider two binary variables a=Number represented by the two rightmost...

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4. Using the dataflow modeling, and consider two binary variables a=Number represented by the two rightmost digits (in Binary) b= Number represented by the third and four digits (in Binary) implement the Verilog code for the below, and show the code and output screenshot. • Bitwise operators • • • Shift operators Case equality Reduction operators Logical operators • Equality 4. Using the dataflow modeling, and consider two binary variables a=Number represented by the two rightmost digits (in Binary) b= Number represented by the third and four digits (in Binary) implement the Verilog code for the below, and show the code and output screenshot. • Bitwise operators • • • Shift operators Case equality Reduction operators Logical operators • Equality 4. Using the dataflow modeling, and consider two binary variables a=Number represented by the two rightmost digits (in Binary) b= Number represented by the third and four digits (in Binary) implement the Verilog code for the below, and show the code and output screenshot. • Bitwise operators • • • Shift operators Case equality Reduction operators Logical operators • Equality 4. Using the dataflow modeling, and consider two binary variables a=Number represented by the two rightmost digits (in Binary) b= Number represented by the third and four digits (in Binary) implement the Verilog code for the below, and show the code and output screenshot. • Bitwise operators • • • Shift operators Case equality Reduction operators Logical operators • Equality

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