$4$ Virtual Memory and Caching

Q$11$: Address Derivation $q,$

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Suppose that you have a System that features the following:

All memory $($RAM and Cache Blocks$)$ is Byte$-$Addressable $($every byte has its own address$).$

The Virtual Address $($VA$)$ is $12$ bits in length.

The size of each Page is $32$ bytes.

The TLB is Direct Mapped $($one entry per set$)$ and can hold $16$ Entries.

The Physical Address $($PA$)$ is $10$ bits in length.

L$1$ Memory Cache is Direct Mapped $($one entry per set$).$

You have $8$ sets in your L$1$ Cache.

The L$1$ Cache Tag is $4$ bits in length.

Each L$1$ Cache Block contains $8$ bytes of data.

The word size is $1$ byte.

Use this information above to answer the following questions:

You can answer with powers of $2($eg$.2^6)$ if more convenient.

$($a$)(1$ point$)$ How many bits are in the VPO part of the VA$?$

$($a$)$

$($b$)(1$ point$)$ How many bits are in the VPN part of the VA$?$

$($b$)$

$($c$)(1$ point$)$ How many Virtual Pages can be in the Page Table?

$($c$)$

$($d$)(1$ point$)$ How many bits are in the TLB Index of the VPN$?$

$$

$($e$)(1$ point$)$ How many bits are in the Cache Index part of the PA$?$

$$

$($f$)(1$ point$)$ How many bits are in the Cache Offset part of the PA$?$

$($f$)$

$($g$)(1$ point$)$ What concept makes Caches effective? $($one word$)$

$(g)$