4.1 All

end loop end Test Bench; (Answers to problems marked with *appear at the end of the b design and its related HDL modeling pr explicitly named, the HDL compiler for solving a problem VHDL. Note: For each problem that requires writing and ve plan should be written to identify which functional features aan and how they will be tested. For example, a reset on-the-fly c PROBLEMS e end of the book. Wherea roblem are cross-referenced may be Verilo ould be t lated machine is in a state other than the reset statT est development of a testbench that will mplement the plan, Simulate the model,iplan ngu and verify that the behavior is correct. 4.1 Consider the combinational circuit shown in Fig. P4.1. (HDLs L-see Problem T3 Ti T2 T4 FIGURE P4.1