4.9 In this exercise, we examine how data dependences affect execution in the basic 5-stage pipeline described in Section 4.5. Problems in this exercise refer to the following sequence of instructions: or r1, r2, r3 or r2, r1, r4 or rl, rl, r2 Also, assume the following cycle times for each of the options related to forwarding: Without Forwarding With Full Forwarding With ALU-ALU Forwarding Only 250 ps 300 ps 290 ps 4.9.1 [10] Indicate dependences and their type. 4.9.2 [10] Assume there is no forwarding in this pipelined processor. Indicate hazards and add nop instruc- tions to eliminate them. 4.9.3 [10] Assume there is full forwarding. Indicate hazards and add nop instructions to eliminate them. 4.9.4 [10] What is the total execution time of this instruction sequence without forwarding and with full for- warding? What is the speedup achieved by adding full for- warding to a pipeline that had no forwarding? 4.9.5 (10] Add nop instructions to this code to elimi- nate hazards if there is ALU-ALU forwarding only (no for- warding from the MEM to the EX stage). 4.9.6 [10] What is the total execution time of this instruction sequence with only ALU-ALU forwarding? What is the speedup over a no-forwarding pipeline