$[50$ points$]$ Textbook, page $276,3\mathrm{.}15.$a$,$ with the latency table below for FUs $($instead of

the latency table in the textbook$)$ and following assumptions in addition to the

assumptions from the textbook:

Only show the first two iterations.

For load$/$store$,$ EX stage is for address calculation and MEM is for memory access.

Each takes one cycle.

The branch outcome is known after the EX stage.

Assume the first fld instruction of the first iteration is issued in cycle $1.$ Fill the

table like this: