$5\mathrm{.}12\mathrm{.}1[10]<5\mathrm{.}4>$ Calculate the CPI for the processor in the table using: $1)$ only a first$-$level cache, $2)$ a second$-$level direct$-$mapped cache, and $3)$ a second$-$level eight$-$way set associative cache. How do these numbers change if main memory access time doubles? $($Give each change as both an absolute CPI and a percent change.$)$ Notice the extent to which an L$2$ cache can hide the effects of a slow memory.

$5\mathrm{.}12\mathrm{.}2[10]<5\mathrm{.}4>$ It is possible to have an even greater cache hierarchy than two levels? Given the processor above with a second$-$level, direct$-$mapped cache, a designer wants to add a third$-$level cache that takes $50$ cycles to access and will have a $13\%$ miss rate. Would this provide better performance? In general, what are the advantages and disadvantages of adding a third$-$level cache?

$5\mathrm{.}12\mathrm{.}3[20]<5\mathrm{.}4>$ In older processors, such as the Intel Pentium or Alpha $21264,$ the second level of cache was external $($located on a different chip$)$ from the main processor and the first$-$level cache. While this allowed for large second$-$level caches, the latency to access the cache was much higher, and the bandwidth was typically lower because the second$-$level cache ran at a lower frequency. Assume a $512$ KiB off$-$chip second$-$level cache has a miss rate of $4\%.$ If each additional $512$ KiB of cache lowered miss rates by $0\mathrm{.}7\%,$ and the cache had a total access time of $50$ cycles, how big would the cache have to be to match the performance of the second$-$level direct$-$mapped cache listed above?