$5\mathrm{.}12\mathrm{.}3[20]<5\mathrm{.}4>$ In older processors, such as the Intel Pentium or

Alpha $21264,$ the second level of cache was external $($located on

a different chip$)$ from the main processor and the first$-$level

cache. While this allowed for large second$-$level caches, the

latency to access the cache was much higher, and the

bandwidth was typically lower because the second$-$level cache

ran at a lower frequency. Assume a $512$ KiB off$-$chip second

level cache has a miss rate of $4\%.$ If each additional $512$ KiB of

cache lowered miss rates by $0\mathrm{.}7\%,$ and the cache had a total

access time of $50$ cycles, how big would the cache have to be to

match the performance of the second$-$level direct$-$mapped

cache listed above?