$5\mathrm{.}26\mathrm{.}1[15]$$$5\mathrm{.}13>$ Which cache design is better for each of these

benchmarks? Use data to support your conclusion.

Off$-$chip bandwidth becomes the bottleneck as

the number of CMP cores increases. How does this bottleneck

affect private and shared cache systems differently? Choose the

best design if the latency of the first off$-$chip link doubles.

$5\mathrm{.}26\mathrm{.}3[10]$ $$5\mathrm{.}13>$ Discuss the pros and cons of shared vs$.$ private

L$2$ caches for both single$-$threaded, multi$-$threaded, and

multiprogrammed workloads, and reconsider them if having

on$-$chip L$3$ caches.

$5\mathrm{.}26\mathrm{.}4[10]$ $$5\mathrm{.}13>$ Would a non$-$blocking L$2$ cache produce more

improvement on a CMP with a shared L$2$ cache or a private L$2$

cache? Why?

$5\mathrm{.}26\mathrm{.}5[10]$ $$5\mathrm{.}13>$ Assume new generations of processors double

the number of cores every $18$ months. To maintain the same

level of per$-$core performance, how much more off$-$chip

memory bandwidth is needed for a processor released in three

years?

Consider the entire memory hierarchy. What

kinds of optimizations can improve the number of concurrent

misses?