Question: 5 . 2 You are considering lowering V D D to try to save power in a static CMOS gate. You will also scale V

5.2 You are considering lowering VDD to try to save power in a static CMOS gate. You will also scale Vt proportionally to maintain performance. Will dynamic power consumption go up or down? Will static power consumption go up or down?
5 . 2 You are considering lowering V D D to try

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