5 3. Develop a bit counter, counting upwards and downwards and test it employing Modelsim software....

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5 3. Develop a bit counter, counting upwards and downwards and test it employing Modelsim software. For development of counter employ signal subtypes count - unsigned (4 downto 0) and output - std_logic_vector(4 downto 0). Keep the source code of fine structure by separating memory cell, next state logic and output logic. (2 points) entity counter is port ( clk in std_logic; ent_up: out output; cnt_down out output); end counter; 5 3. Develop a bit counter, counting upwards and downwards and test it employing Modelsim software. For development of counter employ signal subtypes count - unsigned (4 downto 0) and output - std_logic_vector(4 downto 0). Keep the source code of fine structure by separating memory cell, next state logic and output logic. (2 points) entity counter is port ( clk in std_logic; ent_up: out output; cnt_down out output); end counter;

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The question asks for the development of a 5bit counter in VHDL that can count both upwards and down... View the full answer