$5\mathrm{.}7\mathrm{.}3[15]<5\mathrm{.}4>$ Using the references from Exercise $5\mathrm{.}2,$ what is the miss rate for a fully associative cache with two$-$word blocks and a total size of $8$ words, using LRU replacement? What is the miss rate using MRU $($most recently used$)$ replacement? Finally what is the best possible miss rate for this cache, given any replacement policy? Multilevel caching is an important technique to overcome the limited amount of space that a fi rst level cache can provide while still maintaining its speed. Consider a processor with the following parameters: Base CPI, No Memory Stalls Processor Speed Main Memory Access Time First Level Cache MissRate per Instruction Second Level Cache, Direct$-$Mapped Speed Global Miss Rate with Second Level Cache, Direct$-$Mapped Second Level Cache, Eight$-$Way Set Associative Speed Global Miss Rate with Second Level Cache, Eight$-$Way Set Associative $1\mathrm{.}52$ GHz $100$ ns $7\%12$ cycles $3\mathrm{.}5\%28$ cycles $1\mathrm{.}5\%$