$5.$ Consider the following memory architectures that use a main memory device with a latency of $15$ cycles to retrieve one word of data given a specific row address. Calculate the total latency and bandwidth for each architecture when accessing $16-$word$-$size data. Assume that $16$ words of data are evenly distributed across all banks. Consider the following memory architectures that use a main memory device

with a latency of $15$ cycles to retrieve one word of data given a specific row

address. Calculate the total latency and bandwidth for each architecture when

accessing $16-$word$-$size data. Assume that $16$ words of data are evenly

distributed across all banks

a$.$ Latency: $,$ Bandwidths :

b$.$ Latency: $,$ Bandwidths:

c$.$ Latency: $,$ Bandwidths:

$($a$)$ One word wide memory

$($b$)$ two word wide memory

$($c$)$ One word wide memory with four banks