$5.$ Converting Strings to Lower Case

The figure below shows the datapath for an FSM that converts any upper$-$case letters in an ASCII string to the corresponding lower$-$case letters. An ASCII string consists of a sequence of $\backslash ($ A S C I I $\backslash )$ characters ending in $\backslash (0\backslash$times $00\backslash ),$ the $\backslash ($ A S C I I N U L $\backslash )$ character.

Figure $1$

Inputs for use by external logic, including the STR input, are shown in black. Datapath control signals appear in red. Datapath outputs are shown in blue.

The circuit below shows the next$-$state logic for the FSM that controls the datapath. The START signal is another external control signal used to tell the FSM to start changing the string beginning at the memory location specified by STR into lower case.

Figure $2$

A$.$ The system starts in a WAIT state $\backslash (\backslash$left$($S$\_\{1\}$ S$\_\{0\}=01\backslash$right$.\backslash )),$ allowing external logic to write a string into the memory $($logic not shown$).$ Once the external logic finishes writing the string into the memory $($logic not shown$),$ the external logic provides the starting address of the string through the STR input and raises the START input to make the FSM change any upper$-$case letters in the string to lower case. Using the next$-$state logic and the description above, draw a state transition diagram for the FSM$.$ Draw only those states reachable from the starting state. Transition arcs between states should be drawn without crossing, and should be labeled with the signals START and EOS. START comes from external logic, and EOS $($end of string$)$ comes from the datapath. A transition arc label of $"10,"$ for example, means that START$=1$ and EOS$=0.$ You do not need to label outputs in these states. However, you will need to name each state based on its functionality. Hint $\backslash$#$1$: Make a next$-$state table using the information in Figure $2$ to help you draw the state transition diagram for the FSM$.$ Hint $\backslash$#$2$: To name each state appropriately, consider when state transitions occur and how these transitions relate to the desired operation of your circuit in Figure $1.$

B$.$ Based on the datapath, the state transition diagram from part $($a$),$ and the desired operation of the FSM$,$ calculate the three datapath control signals for each state $($AMUX$,$ A$.$LD$,$ and M$.$WE$).$ Note that you may need to use the datapath output signals EOS and$/$or $\backslash ($ U $\backslash )$ when calculating the control signals for the states. Also, notice that it takes one additional clock cycle to update the value in the $8-$bit register $($which holds the ASCII character represented in binary$)$ based on when the address is stored in the N$-$bit register. One more thing, consider any unused states and what the datapath control signals should be if we were to somehow enter that state.

C$.$ Based on your answers to part $($b$),$ find expressions with optimal area to express each datapath control signal $($AMUX$,$ A$.$LD$,$ and M$.$WE$)$ in terms of the current state $\backslash (\backslash$mathrm$\{$S$\}\_\{1\}\backslash$mathrm$\{$~S$\}\_\{0\}\backslash )$ and the datapath output signals EOS and $\backslash ($ U $\backslash ).$