Question: 5. For this question you will answer questions about Verilog coding and timing diagrams module codeA output reg (1:0) out_sig, input wire clk, input wire

5. For this question you will answer questions about Verilog coding and timing diagrams module codeA output reg (1:0) out_sig, input wire clk, input wire clr, a) Based on the code on the right, list the inputs and outputs below. Indicate any busses and the size of each bus found. always (posedge clk or posedge cir) pe (clr MB) out sig

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