5) Problem 3.9 text - sketch the S1, RI, and Q output signals for the NOR SR latch, including the NOT USED cases (use dashed lines for NOT USED cases) 3.9 Trace the behavior of a level-sensitive SR latch (see Figure 3.16) for the input pattern in Figure 3.96. Assume s1, R1, and O are initially o. Complete the timing diagram, assuming logic gates have a tiny but nonzero delay S1 R1 Figure 3.96 SR latch input patern timing diagram