$[5$ pts $+2$ extra pt$]$ Exercise $9\mathrm{.}8$: Procedure mean$\_$and$\_$median

Write a procedure that receives three $8-$bit STD$\_$LOGIC$\_$VECTOR signals and returns their arithmetic mean and their median, of the same type. The system should be considered to be signed. Install your procedure in the declarative part of the ARCHITECTURE $($main code$).$ In the code proper $($architecture body$),$ include a call to that procedure in order to test $($simulate$)$ it$.$

$--$ copy your formatted plain VHDL code with header here; Use code from

Pedroni book $2/$e page $164$ as starting point

$[2$ extra pts$]$ Verify via simulation using $10$ sets of data

$--$ copy your formatted plain text DO file and simulation with esignature here; use DO file from previous HW as starting point. Replace the following picture with your simulation.